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Regular Expression-based System Verilog signal extractor

technology1 mentionslast seen Sep 16, 2026

A lightweight tool proposed to identify signals for generating security assertions and prevent signal hallucination.

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AutoTransimplementsRegular Expression-based System Verilog signal extractor85% confidence1 source

Regular Expression-based System Verilog signal extractor

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AutoTransimplementsRegular Expression-based System Verilog signal extractor

85% confidence1 supporting mentions

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preprintarXivSep 9, 2026AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
AutoTrans, an automated framework that addresses the above shortcomings. First, a new lightweight Regular Expression-based System Verilog signal extractor is proposed